| Package Type |
DIP |
| Notes |
Motor Control, Through Hole, Bulk, DSP (Digital Signal Processors) |
| Abstract |
The ADMCF326 uses an input clock with a
frequency equal to half the instruction rate; a 10 MHz input clock (equivalent to
100 ns) yields a 50 ns processor cycle (equivalent to 20 MHz). When tCK values are
within the range of 0.5 tCKIN period, they should be substituted for all relevant
timing parameters to obtain specification value.
Example: tCKH = 0.5 tCK 10 ns = 0.5 (50 ns) 10 ns = 15 ns. Timing Requirements:
tCKIN CLKIN Period 100 150 ns tCKIL CLKIN Width Low 20 ns tCKIH CLKIN Width High 20 ns
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