Digital Latches

Digital latches are logic devices that latch onto or retain digital states (1 or 0) in data storage circuits. Because they use sequential logic, digital latches control and are controlled by other circuitry in a specific sequence that is determined by a control clock and enable/disenable control signals. Latches, which represent the simplest form of data storage, sometimes have an enable input that is used to control the latch, or to accept or ignore the input stage. Latch outputs respond immediately to changes at the input. Several types of digital latches are available. Data (D) and transparent D latches have a data input. S-R latches have either set (S) and reset (R) inputs, or set (S) and clear (C) inputs. Gate S-R latches have an enable input. Digital latches that contain an array of latches, each of which can be programmed, are also available.  

Digital latches vary in terms of supply voltage, operating current, propagation delay, power dissipation, low level output current (sink), high level output current (source), and output characteristics. Supply voltages range from - 5 V to 5 V and include intermediate voltages such as  -4.5 V, -3.3 V, -3 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3 V, 3.3 V, and 3.6 V. The operating current is the minimum current needed for active operation. The propagation delay is the time interval between the application of an input signal and the occurrence of the corresponding output. Power dissipation, the total power consumption of the device, is generally expressed in watts or milliwatts. The low-level output current (IOL) is the output current to which gates sink. The high-level output current (IOH) is the output current that gates source to a load. Three-state, open-collector, open-drain, and complementary outputs are available. Output enable (OE) inputs have an enable pin for the output. 

Selecting digital latches requires an analysis of logic families. Transistor-transistor logic (TTL) and related technologies such as Fairchild advanced Schottky TTL (FAST) use transistors as digital switches. By contrast, emitter coupled logic (ECL) uses transistors to steer current through gates that compute logical functions. Another logic family, complementary metal-oxide semiconductor (CMOS), uses a combination of p-type and n-type metal-oxide-semiconductor field effect transistors (MOSFETs) to implement logic gates and other digital circuits. Logic families for digital latches include cross-bar switch technology (CBT), Gallium arsenide (GaAs), integrated injection logic (I²L) and silicon on sapphire (SOS). Gunning with transceiver logic (GTL) and gunning with transceiver logic plus (GTLP) are also available.

Digital latches are available in a variety of IC package types and with different numbers of pins and flip-flops. Basic IC package types for digital latches include ball grid array (BGA), quad flat package (QFP), single in-line package (SIP), and dual in-line package (DIP). Many packaging variants are available. For example, BGA variants include plastic-ball grid array (PBGA) and tape-ball grid array (TBGA). QFP variants include low-profile quad flat package (LQFP) and thin quad flat package (TQFP). DIPs are available in either ceramic (CDIP) or plastic (PDIP). Other IC package types include small outline package (SOP), thin small outline package (TSOP), and shrink small outline package (SSOP).

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