Complex Programmable Logic Devices (CPLD)

Complex programmable logic devices (CPLDs) are integrated circuits (ICs) or chips that application designers configure to implement digital hardware such as mobile phones. CPLDs can handle significantly larger designs than simple programmable logic devices (SPLDs), but provide less logic than field programmable gate arrays (FPGAs). CPLDs contain several logic blocks, each of which includes eight to 16 macrocells. Because each logic block performs a specific function, all of the macrocells within a logic block are fully connected. Depending upon the application, however, logic blocks may or may not be connected to one another. 

Most complex programmable logic devices contain macrocells with a sum-of-product combinatorial logic function and an optional flip-flop. Depending on the CPLD, the combinatorial logic function supports from four to sixteen product terms with wide fan-in. Complex programmable logic devices also vary in terms of logic gates and shift registers. For this reason, CPLDs with a large number of logic gates may be used in place of FPGAs. Another CPLD specification denotes the number of product terms that a macrocell can manage. Product terms are the product of digital signals that perform a specific logic function.

Complex programmable logic devices are available in many IC package types and logic families. CPLDs also vary in terms of supply voltage, operating current, standby current, and power dissipation. In addition, CPLDs are available with different amounts of memory and different types of memory support. Typically, memory is expressed in bits or megabits. Memory support includes read-only memory (ROM), random access memory (RAM), and dual-port RAM. It also includes content addressable memory (CAM) as well as first-in, first-out (FIFO) memory and last-in, last-out (LIFO) memory. 

There are several performance specifications for complex programmable logic devices. Internal frequency is the speed at which CPLDs can perform operations or transfer data internally. The propagation delay is the time interval between the application of an input signal and the occurrence of the corresponding output in a logic circuit. Speed grade indicates the delay in nanoseconds (ns) through a macrocell in the device. For example, a device with a speed grade of –10 has a delay of 10 ns through a macrocell. Devices with low speed grade numbers run faster than devices with high-speed grade numbers.

Some complex programmable logic devices include integrated phase-locked loops (PLLs) and delay-locked loops (DLLs) with clock-frequency-synthesis capabilities so that designers can use CPLDs for system-on-chip applications. PLL and DLL clock multiplication also allows designers to generate a high-speed internal clock for sampling data in digital signal processing (DSP) applications. In addition, PLLs and DLLs provide greater control over the clock frequencies used in integrated designs. This is critical for system integration because different parts of a system operate at different clock frequencies.

Complex programmable logic devices feature predictable timing characteristics that make them ideal for critical, high-performance control applications. Typically, CPLDs have a shorter and more predictable delay than FPGAs and other programmable logic devices. Because they are inexpensive and require relatively small amounts of power, CPLDs are often used in cost-sensitive, battery-operated portable applications. CPLDs are also used in simple applications such as address decoding.

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  The first section of this paper describes the development of limitations in I/O connectivity and logic reusability in Complex Programmable Logic Devices (CPLDs) over their 20- year history. The second...
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Part Numbers for Complex Programmable Logic Devices CPLD