ASIC chips (application specific integrated circuits) are designed for a specific application. An ASIC chip is a type of integrated circuit, often referred to as "gate-array" or "standard-cell" products, developed and designed to satisfy a specific application requirement. Standards cells are used in ASIC design. An ASIC engineer can create functional blocks with known electrical characteristics, such as propagation delay, capacitance and inductance, which can also be represented in third party tools. Standard cell design is the utilization of these functional blocks to achieve very high gate density and good electrical performance. Standard cell design falls between gate array and full custom design in terms of both the non-recurring engineering and recurring component cost. An FPGA ASIC (field-programmable gate array, application specific integrated circuit) design is a specially made digital semiconductor often used for ASIC prototyping. With this method, an ASIC engineer is able to program electrical connections for a specific application (for example a device for a sound/video card), without having the chip manufactured in mass quantities. A structured ASIC is an integrated circuit with predefined blocks that is programmed by customizing the top two to five routing layers. Other ASIC chips are commonly available.

There are many methods for designing and producing ASIC chips. Modern application specific integrated circuit chips often include entire 32-bit processors and other large building-blocks. This type of ASIC chip is often referred to as a system-on-a-chip (SoC). Design flow of ASIC chips is highly automated. These automation tools provide reasonable performance and cost advantage over a manual design process. ASIC design can be divided into following sections: register-transfer level (RTL) description, simulation, syntheses, extraction, and physical verification. A hierarchy of programmable interconnects allows the logic blocks of an FPGA ASIC chip to be interconnected by an ASIC engineer, similar to a one-chip programmable breadboard. The logic blocks and interconnects can be programmed after the manufacturing process by an ASIC engineer so that the FPGA ASIC chip can perform whatever logical function is needed. A structured ASIC provides reduced entry cost and faster time to silicon by using a predefined arrangement of late-stage, mask-customizable logic and prediffused macros and IP. With the integration of increasing system components on single ASIC chips, the complexity of ASIC prototyping has increased. System design involves complex layout issues. Specifications of cells are provided by the vendors in form of a technology library which contains information about geometry, delay, and power characteristics of cells. ASIC chips are designed and manufactured to meet most industry specifications.

ASIC chips (application specific integrated circuits) are designed for a specific application. An ASIC chip is a type of integrated circuit, often referred to as "gate-array" or "standard-cell" products, developed and designed to satisfy a specific application requirement. Standards cells are used in ASIC design. An ASIC engineer can create functional blocks with known electrical characteristics, such as propagation delay, capacitance and inductance, which can also be represented in third party tools. Standard cell design is the utilization of these functional blocks to achieve very high gate density and good electrical performance. Standard cell design falls between gate array and full custom design in terms of both the non-recurring engineering and recurring component cost. An FPGA ASIC (field-programmable gate array, application specific integrated circuit) design is a specially made digital semiconductor often used for ASIC prototyping. With this method, an ASIC engineer is able to program electrical connections for a specific application (for example a device for a sound/video card), without having the chip manufactured in mass quantities. A structured ASIC is an integrated circuit with predefined blocks that is programmed by customizing the top two to five routing layers. Other ASIC chips are commonly available.

There are many methods for designing and producing ASIC chips. Modern application specific integrated circuit chips often include entire 32-bit processors and other large building-blocks. This type of ASIC chip is often referred to as a system-on-a-chip (SoC). Design flow of ASIC chips is highly automated. These automation tools provide reasonable performance and cost advantage over a manual design process. ASIC design can be divided into following sections: register-transfer level (RTL) description, simulation, syntheses, extraction, and physical verification. A hierarchy of programmable interconnects allows the logic blocks of an FPGA ASIC chip to be interconnected by an ASIC engineer, similar to a one-chip programmable breadboard. The logic blocks and interconnects can be programmed after the manufacturing process by an ASIC engineer so that the FPGA ASIC chip can perform whatever logical function is needed. A structured ASIC provides reduced entry cost and faster time to silicon by using a predefined arrangement of late-stage, mask-customizable logic and prediffused macros and IP. With the integration of increasing system components on single ASIC chips, the complexity of ASIC prototyping has increased. System design involves complex layout issues. Specifications of cells are provided by the vendors in form of a technology library which contains information about geometry, delay, and power characteristics of cells. ASIC chips are designed and manufactured to meet most industry specifications.

ASIC chips are used in used in a variety of applications. Examples include timer electronics, mobile phone control circuits, interface and signaling processing electronics for sensors, control and evaluation circuit for motion detectors, high voltage operational amplifier. Analog ASIC chips developed for use in industrial environments have to meet output requirements. If high output currents are necessary, an internal protection against excess temperature, or for current limitation, can be designed into the ASIC chips.