FIFO Memory

First-in, first-out (FIFO) memory chips are used in buffering applications between devices that operate at different speeds, or in applications where data must be stored temporarily for further processing. Typically, this type of buffering is used to increase bandwidth and to prevent data loss during high-speed communications. As the term FIFO implies, data is released from the buffer in the order of its arrival. Some FIFO memory reads with one clock and writes with another simultaneously. Synchronous operations require a clock, but asynchronous operations do not. Flow control generates full and empty signals so that inputs do not overwrite the contents of the buffer. Depending on the device, FIFO memory can be unidirectional or bidirectional. FIFO memory can also include parallel inputs and outputs as well as programmable flags.

FIFO memory varies in terms of density, number of words, bits per word, supply voltage, and operating temperature. The density is the capacity of the chip in bits. The number of words equals the number of rows, each of which stores a memory word and connects to a word line for addressing purposes. Bits per word is the number of columns, each of which connects to a sense/write circuit. Supply voltages range from - 5 V to 5 V and include intermediate voltages such as  -4.5 V, -3.3 V, -3 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3 V, 3.3 V, and 3.6 V. Some FIFO memory chips support a specific temperature range and feature mechanical and electrical specifications that are suitable for commercial or industrial applications. Other FIFO memory chips meet screening levels for military specifications (MIL-SPEC).

Selecting FIFO memory requires an analysis of performance specifications such as access time, data rate, data setup time, and data hold time. Measured in nanoseconds (ns), access time indicates the speed of memory and represents a cycle that begins when the CPU sends a request to memory and ends when the CPU receives the data requested. The data rate or transfer speed is the number of bits per second in hertz (Hz) that can be moved internally in the chip. The data setup time is the minimum time interval required for logic levels to be maintained constantly in the input lines prior to the triggering edge of the clock pulse in order for the levels to be reliably clocked into the memory. The data hold time is the minimum time interval required for logic levels to remain on the inputs after the triggering edge of the clock pulse in order to be reliably clocked into the chip.

FIFO memory chips vary in terms of logic family and IC package type. Common logic families include standard, fast, high-speed and advanced CMOS; emitter coupled logic (ECL); TTL and Fairchild advanced Schottky TTL (FAST); gunning technology (GTL); and crossbar switch technology (CBT). Common package types include ball grid array (BGA), quad flat package (QFP), single in-line package (SIP), and dual in-line package (DIP). Many packaging variants are available for FIFO chips. Common packaging materials include plastic, ceramic, metal, and glass.

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Part Numbers for FIFO Memory