Analog-to-digital converter (ADC) chips transform information from analog to digital form. ADC chips receive analog input, perform calculations on the analog signal, and then digitally encode the output in a format that computerized systems can process. Analog-to-digital converter (ADC) chips are used in a variety of applications, including data-acquisition, communications, instrumentation, and signal processing. To cover a broad range of performance needs, ADCs are available in different resolutions, bandwidths, accuracies, packaging, power requirements, and temperature ranges.
Successive-approximations register (SAR) and Flash are two common architectures for analog-to-digital converter (ADC) chips. SAR architecture uses a single comparator and multiple conversion cycles. Flash, or parallel, architecture uses multiple comparators and a single conversion cycle. With flash, ADC chips use a set of 2n-1 comparators to measure an analog signal to a resolution of n bits. Consequently, flash ADC chips are faster than SAR ADC chips, but require a greater number of comparators.
Pipeline architecture overcomes some of the limitations of Flash architecture by dividing the conversion task into several consecutive stages. Each stage consists of a sample and hold circuit, an m-bit ADC (e.g., a flash converter), and an m-bit digital-to-analog converter (DAC). In this way, pipelined converters achieve higher resolutions than flash converters containing a similar number of comparators. However, pipeline analog-to-digital converter (ADC) chips increase the total conversion time from one cycle to p cycles.
Subranging, another approach for analog-to-digital converter (ADC) chips, combines Flash, SAR, and pipeline architectures and breaks n-bit conversions into m-bit sub-conversions. Like pipeline architecture, sub-ranging consists of several cascading stages, each of which uses a low-resolution ADC chip to estimate the input and an accurate DAC to convert the output. Subranging also calculates the residue, the difference between the estimated input and the actual output. A gain block is used to amplify and restore the residue to an appropriate level for further estimation by the next stage.
Sigma-delta architecture for analog-to-digital converter (ADC) chips takes a fundamentally different approach than other ADC architectures. Sigma-delta converters consist of an integrator, a comparator, and a single-bit DAC. The DAC output is subtracted from the input signal, the resulting signal is integrated, and the comparator converts the integrator output voltage to a single-bit digital output (1 or 0). The resulting bit becomes the DAC’s input, and the DAC’s output is subtracted from the ADC chip input signal. With sigma-delta architecture, the digital data from the ADC chip is a stream of ones and zeros, and the value of the signal is proportional to the density of digital ones from the comparator. This bit stream data is then digitally filtered and decimated to result in a binary-format output.
In terms of performance, analog-to-digital converter (ADC) chips vary according to resolution, sample rate, input voltage range, operating temperature, and a number of other variables. Signal-to-noise (SNR) ratios and signal-to-noise distortion (SINAD) ratios are decibel amounts that represent RMS values for the sine wave fIN. Differential non-linearity (DNL) errors measure the differences between ideal and measured code transitions for successive ADC codes. DNL errors also measure the difference between ideal and measured output values for successive DAC codes. Integrated non-linearity (INL) is the amount of deviation of the measured transfer function of analog-to-digital converter (ADC) chips or digital-to-analog converter (DAC) chips from the ideal transfer function.
More >>
